A cyclic A/D converter operates at relatively high speed with a relatively small scale circuit and is a well-known approach suitable for high resolution. FIG. 1 shows an example of a conventional circuit of an cyclic A/D converter. This circuit performs amplification of the gain of 2 per one stage of unit circuits. In response to a result of a comparator in each unit circuit, the circuit performs addition or subtraction operation of a reference voltage. Two bit A/D conversion per one clock can be provided in the circuit in which two stages are connected in cascade arrangement and the output of the cascaded stages is connected to its input. The five-times repetition of this A/D conversion provides a 10 bit A/D conversion result.
Since such a cyclic A/D converter has relatively simple circuitry, an array of cyclic A/D converters can be integrated into the column of an image sensor array as shown in Non-Patent Document 1.
Patent Document 1 discloses a circuit which can perform noise cancellation as well as cyclic A/D conversion using one amplifier as shown in FIG. 2.
Non-Patent Document 2 discloses a method for canceling major components of random noise using a high gain amplifier to reduce the random noise and performing the cancellation of noise generated in pixels.
A circuit in Patent Document 2 reduces a fixed pattern noise using a noise canceling circuit including a two amplifying stages. Moreover, this circuit is characterized in that active devices, such as a switch, are not used in conjunction with the capacitor coupled between the input and output of the first amplifying stage.
In Patent Document 3, cyclic A/D conversion of a signal voltage containing noise is performed to generate a digital value and it is stored in the first register, while cyclic A/D conversion of a signal voltage containing noise and a signal from an optical signal is performed to generate a digital value and it is stored in the second register, and then the noise is canceled by the operation of these values.
In the cyclic A/D converter of Patent Document 4, the input terminal of a parallel type A/D converter circuit is selectively coupled to either a signal input terminal or an output terminal of an operational amplifier via a switch. While one ends of capacitors in a capacitor array are coupled together to a common line, other ends of the capacitors are selectively coupled to an input terminal of the A/D converter circuit, a reference voltage terminal and a ground terminal via respective switches. Patent Document 5 discloses a sample/hold circuit using a differential amplifier circuit.
[Patent Document 1] Japanese Patent Application Laid-open No. 2005-136540
[Patent Document 2] U.S. Pat. No. 6,128,039
[Patent Document 3] Japanese Patent Application Laid-open No. 2006-25189
[Patent Document 4] Japanese Patent Application Laid-open No. 2001-53610
[Patent Document 5] Japanese Patent Application Laid-open No. 2003-158432
[Non-Patent Document 1] S. Decker and R. D. Mcgrath, K. Brehmer and C. G. Sodini, “A 256×256 CMOS imaging array with wide dynamic range pixels and column parallel digital output”, IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2081-2091, December 1998
[Non-Patent Document 2] N. Kawai and S. Kawahito, “Noise analysis of high gain low noise column readout circuits for CMOS image sensors”, IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 185-194 (2004)